BCM5421S | ||||||||
BCM5421S ManufacturerBCM5421S DescriptionBCM5421S CategoriesBCM5421S Datasheet (PDF)BCM5421S Price & AvailabilityBCM5421S Features
BCM5421S DescriptionThe BCM5421S's Digital Signal Processor based architecture and advanced power management techniques combine to achieve robust and low power operation over the existing CAT 5 twisted pair wiring. The BCM5421S architecture not only meets the requirements of 802.3, 802.3u, and 802.3ab, but maintains the industry's highest level of margin over IEEE requirements for Echo, NEXT, and FEXT. Low power is a key factor in implementing Gigabit small form factor GBICs and uplinks and, at 1W per port, the BCM5421S dissipates nearly half the power of previous Gigabit PHY transceivers. In addition, the BCM5421S has extremely low EMI emissions, which reduces the design constraints required to meet EMI emissions specifications. In addition to supporting IEEE 802.3 Standard Gigabit Media Independent Interface (GMII), and industry standard Ten Bit Interface (TBI), the BCM5421S also supports the RGMII and RTBI, serial SerDes, and SGMII interfaces. The serial SerDes and SGMII are reduced pin-count (4 band 6 respectively, versus 25) Switch/MAC interfacees. In addition, the serial SerDes interface can be used to route from SerDes to copper as in GBIC applications. RGMII is a reduced pin-count (12 versus 25) version of the GMII and RTBI is a reduced pin-count version of TBI utilizing standard ASIC technology. The high-density package, multiple MAC interfaces, and streamlined power supply lowers system cost and simplifies the system and board level design. Keywords
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