CS8900A Datasheet

Single-chip IEEE 802.3 Ethernet solution
Comprehensive suite of software drivers available
Efficient PacketPage architecture operates in I/O and memory space and as DMA slave
Full-duplex operation
On-chip RAM buffers transmit and receive frames
10Base-T port and filters (polarity detection/correction)
AUI port for 10Base-2, 10Base-5, and 10Base-F
Automatic re-transmission on collision, padding, and CRC (cyclical redundancy check)
Programmable receive features
- Stream transfer for reduced CPU overhead
- Auto-switch between DMA and on-chip memory
- Early interrupts for frame pre-processing
- Automatic rejection of erroneous packets
EEPROM support for jumperless configuration
Boot PROM support for diskless systems
Boundary scan and loopback test
LED drivers for link status and LAN activity
Standby and suspend sleep modes
3 V or 5 V operation; commercial or industrial temperature range
Maximum at 5 V = 120 mA; typical at 5 V = 90 mA
Package: 100-pin TQFP; option for lead-free assembly

CS8900A