| 5962-87539013X Description | | 18-Mb Burst of 4 Pipelined SRAM with QDR™ Architecture | | 5962-87539013X Vendor | | Cypress | | 5962-87539013X Features | - Separate independent Read and Write data ports
- Supports concurrent transactions
- 167-MHz clock for high bandwidth
- 2.5 ns Clock-to-Valid access time
- 4-Word Burst for reducing the address bus frequency
- Double Data Rate (DDR) interfaces on both Read & Write Ports (data transferred at 333 MHz) @167 MHz
- Two input clocks (K and K) for precise DDR timing
- SRAM uses rising edges only
- Two output clocks (C and C) accounts for clock skew and flight time mismatching
- Single multiplexed address input bus latches address inputs for both Read and Write ports
- Separate Port Selects for depth expansion
- Synchronous internally self-timed writes
- 2.5V core power supply with HSTL Inputs and Outputs
- 13 x 15 x 1.2 mm 1.0-mm pitch fBGA package, 165 ball (11x15 matrix)
- Variable drive HSTL output buffers
- Expanded HSTL output voltage (1.4V–1.9V)
- JTAG Interface
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