CY62126BV

CY62126BV Manufacturer

CY62126BV Description

CY62126BV Categories

CY62126BV Datasheet (PDF)

CY62126BV Price & Availability

CY62126BV Features

• High Speed: 55 ns and 70 ns
• Wide voltage range: 2.7V?3.6V operation
• Low active power (70 ns, LL version)
  • 54 mW (max.) (15 mA)
• Low standby power (70 ns)
  • 54 µW (max.) (15 µA)
• Easy memory expansion with /CE and /OE features
• Automatic power-down when deselected
• CMOS for optimum speed/power
• Package available in a 44-pin TSOP II (forward) and a 48 ball fBGA package

CY62126BV Description

The CY62126BV MoBL^® is a high-performance CMOS static RAM organized as 64K words by 16 bits. This device has an automatic power-down feature that significantly reduces power consumption by 99% when deselected. The device enters power-down mode when /CE is HIGH.

Writing to the device is accomplished by taking Chip Enable (/CE) and Write Enable (/WE) inputs LOW. If Byte Low Enable (/BLE) is LOW, then data from I/O pins (I/O₁ through I/O₈), is written into the location specified on the address pins (A₀ through A₁₅). If Byte High Enable (/BHE) is LOW, then data from I/O pins (I/O₉ through I/O₁₆) is written into the location specified on the address pins (A₀ through A₁₅).

Reading from the device is accomplished by taking Chip Enable (/CE) and Output Enable (/OE) LOW while forcing the write enable (/WE) HIGH. If Byte Low Enable (/BLE) is LOW, then data from the memory location specified by the address pins will appear on I/O₁ to I/O₈. If Byte High Enable (/BHE) is LOW, then data from memory will appear on I/O₉ to I/O₁₆. See the truth table at the back of this data sheet for a complete description of read and write modes.

The input/output pins (I/O₁ through I/O₁₆) are placed in a high-impedance state when the device is deselected (/CE HIGH), the outputs are disabled (/OE HIGH), the /BHE and /BLE are disabled (/BHE, /BLE HIGH), or during a write operation (/CE LOW, and /WE LOW).

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