CY62126DV30L-55BVI

CY62126DV30L-55BVI Manufacturer

CY62126DV30L-55BVI Description

CY62126DV30L-55BVI Datasheet (PDF)

CY62126DV30L-55BVI Price & Availability

CY62126DV30L-55BVI Features

• Typical active current: 0.85 mA @ f = 1 MHz
• Typical active current: 5 mA @ f = fMAX

CY62126DV30L-55BVI Description

The CY62126DV30 is a high-performance CMOS static RAM organized as 64K words by 16 bits. This device features advanced circuit design to provide ultra-low active current. This is ideal for providing More Battery Life? (MoBLŽ) in portable applications such as cellular telephones. The device also has an automatic power-down feature that significantly reduces power consumption by 90% when addresses are not toggling. The device can be put into standby mode reducing power consumption by more than 99% when deselected Chip Enable (/CE) HIGH. The input/output pins (I/O0 through I/O15) are placed in a high-impedance state when: deselected Chip Enable (/CE) HIGH, outputs are disabled (/OE HIGH), both Byte High Enable and Byte Low Enable are disabled (/BHE, /BLE HIGH) or during a Write operation (Chip Enable (/CE) LOW and Write Enable (/WE) LOW).

Writing to the device is accomplished by taking Chip Enable (/CE) LOW and Write Enable (/WE) input LOW. If Byte Low Enable (/BLE) is LOW, then data from I/O pins (I/O0 through I/Oh A15). If Byte High Enable (/BHE) is LOW, then data from I/O pins (I/O8 through I/O15) is written into the location specified on the address pins (A0 through A15).

CY62126DV30L-55BVI Parameters

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