Catalog Categories Part Numbers All Datasheets

CY62128DV30 Datasheet

CY62128DV30 ManufacturerCypress
CY62128DV30 Description1 Mb (128K x 8) Static RAM
CY62128DV30 Categories
128Kx8 SRAM
CY62128DV30 Datasheet (PDF)
CY62128DV30 Datasheet
CY62128DV30 Features
  • Very high speed:  55 and 70 ns
  • Wide voltage range:  2.2V to 3.6V
  • Pin compatible with CY62128V
  • Ultra-low active power
    • Typical active current: 0.85 mA @ f = 1 MHz
    • Typical active current: 5 mA @ f = fMAX
  • Ultra-low standby power
  • Easy memory expansion with /CE1, CE2, and /OE features
  • Automatic power-down when deselected
  • Packages offered in a 32-lead SOIC, a 32-lead TSOP, a 32-lead Short TSOP, and a 32-lead Reverse TSOP
CY62128DV30 Description

    The CY62128DV30 is a high-performance CMOS static RAM organized as 128K words by 8 bits. This device f eatures ad­vanced circuit design to provide ultra-low active current. This is ideal for providing More Battery LifeTM (MoBL®) in portable applications such as cellular telephones. The device also has an automatic power-down feature that significantly reduces power consumption by 90% when addresses are not toggling. The device can be put into standby mode reducing power con­sumption by more than 99% when deselected Chip Enable 1 (/CE1) HIGH or Chip Enable 2 (CE2) LOW . The input/output pins (I/O0 through I/O7) are placed in a high-impedance state when: deselected Chip Enable 1 (/CE1) HIGH or Chip Enable 2 (CE2) LOW , outputs are disabled (/OE HIGH),  or during a write operation (Chip Enable 1 (/CE1) LOW and Chip Enable 2 (CE2) HIGH  and Write Enable (/WE) LOW).

    Writing to the device is accomplished by taking Chip Enable 1 (/CE1) LOW with Chip Enable 2 (CE2) HIGH and Write En­able (/WE) LOW. Data on the eight I/O pins is then written into the location specified on the Address pin (A0 thro. A16).

    Reading from the device is accomplished by taking Chip En­able 1 (/CE1) LOW with Chip Enable 2 (CE2) HIGH and Output Enable (/OE) LOW while forcing the Write Enable (/WE) HIGH. Under these conditions, the contents of the memory location specified by the address pins will appear on the I/O pins.

    The eight input/output pins (I/Oo through I/O7) are placed in a high-impedance state when the device is deselected (/CE1 HIGH or CE2 LOW), the outputs are disabled (/OE HIGH) or during a write operation (/CE1 LOW, CE2 HIGH), and /WE LOW).

     

     

    Related or Similar ComponentsCY62128DV30L-55SI CY62128DV30L-55ZAI CY62128DV30L-55ZI CY62128DV30L-55ZRI CY62128DV30LL-55SI CY62128DV30LL-55ZAI CY62128DV30LL-55ZI CY62128DV30LL-55ZRI CY62128DV30LL-70SI CY62128DV30LL-70ZAI CY62128DV30LL-70ZI CY62128DV30LL-70ZRI
    CY62128DV30 Data Sheet CY62128DV30 Spec CY62128DV30 Application Notes CY62128DV30 Distributor
    CY62128DV30 Datenblatt CY62128DV30 Fiche Technique CY62128DV30 Описание CY62128DV30 Даташит
    CY62128DV30 Circuit CY62128DV30 RoHS CY62128DV30 Vendor CY62128DV30 Reference
    Datasheets