The CY62128DV30 is a high-performance CMOS static RAM organized as 128K words by 8 bits. This device f eatures ad­vanced circuit design to provide ultra-low active current. This is ideal for providing More Battery Life^TM (MoBL^®) in portable applications such as cellular telephones. The device also has an automatic power-down feature that significantly reduces power consumption by 90% when addresses are not toggling. The device can be put into standby mode reducing power con­sumption by more than 99% when deselected Chip Enable 1 (/CE1) HIGH or Chip Enable 2 (CE2) LOW . The input/output pins (I/O0 through I/O7) are placed in a high-impedance state when: deselected Chip Enable 1 (/CE1) HIGH or Chip Enable 2 (CE2) LOW , outputs are disabled (/OE HIGH),  or during a write operation (Chip Enable 1 (/CE1) LOW and Chip Enable 2 (CE2) HIGH  and Write Enable (/WE) LOW).

Writing to the device is accomplished by taking Chip Enable 1 (/CE₁) LOW with Chip Enable 2 (CE₂) HIGH and Write En­able (/WE) LOW. Data on the eight I/O pins is then written into the location specified on the Address pin (A₀ thro. A₁₆).

Reading from the device is accomplished by taking Chip En­able 1 (/CE₁) LOW with Chip Enable 2 (CE₂) HIGH and Output Enable (/OE) LOW while forcing the Write Enable (/WE) HIGH. Under these conditions, the contents of the memory location specified by the address pins will appear on the I/O pins.

The eight input/output pins (I/O_o through I/O₇) are placed in a high-impedance state when the device is deselected (/CE₁ HIGH or CE₂ LOW), the outputs are disabled (/OE HIGH) or during a write operation (/CE₁ LOW, CE₂ HIGH), and /WE LOW).