CY62128VLL-70SC

CY62128VLL-70SC Manufacturer

CY62128VLL-70SC Description

CY62128VLL-70SC Description

CY62128VLL-70SC Datasheet (PDF)

CY62128VLL-70SC Price & Availability

CY62128VLL-70SC Features

• High speed: 55 ns and 70 ns
• Wide voltage range: 2.7V?3.6V
• Low active power and standby power
• Easy memory expansion with /CE₁, CE₂ and /OE features
• TTL-compatible inputs and outputs
• Automatic power-down when deselected
• CMOS for optimum speed/power
• Package is available in a standard 450-mil-wide 32-lead SOIC, 32-lead TSOP-I, 32-lead reverse TSOP-1, and 32-lead STSOP-1 package

CY62128VLL-70SC Description

The CY62128V is composed of high-performance CMOS static RAMs organized as 128K words by 8 bits. Easy memory expansion is provided by an active LOW Chip Enable (/CE₁), an active HIGH Chip Enable (CE₂), an active LOW Output Enable (/OE) and three-state drivers. These devices have an automatic power-down feature, reducing the power consumption by over 99% when deselected.

Writing to the device is accomplished by taking Chip Enable one (/CE₁) and Write Enable (/WE) inputs LOW and the Chip Enable two (CE₂) input HIGH. Data on the eight I/O pins (I/O₀ through I/O₇) is then written into the location specified on the address pins (A₀ through A₁₆).

Reading from the device is accomplished by taking Chip Enable one (/CE₁) and Output Enable (/OE) LOW while forcing Write Enable (/WE) and Chip Enable two (CE₂) HIGH. Under these conditions, the contents of the memory location specified by the address pins will appear on the I/O pins.

The eight input/output pins (I/O₀ through I/O₇) are placed in a high-impedance state when the device is deselected (/CE₁ HIGH or CE₂ LOW), the outputs are disabled (/OE HIGH), or during a write operation (/CE₁ LOW, CE₂ HIGH, and /WE LOW).

CY62128VLL-70SC Parameters

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