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CY62136CV Datasheet

CY62136CV ManufacturerCypress
CY62136CV Description2-Mbit (128K x 16) Static RAM
CY62136CV Categories
128Kx16 SRAM
CY62136CV Datasheet (PDF)
CY62136CV Datasheet
CY62136CV Features
  • Very high speed: 55 ns and 70 ns
  • Voltage range:
    • CY62136CV30: 2.7V?3.3V
    • CY62136CV33: 3.0V?3.6V
    • CY62136CV: 2.7V?3.6V
  • Pin-compatible with the CY62136V
  • Ultra-low active power
    • Typical active current: 1.5 mA @ f = 1 MHz
    • Typical active current: 5.5 mA @ f = fmax (70-ns speed)
  • Low standby power
  • Easy memory expansion with /CE and /OE features
  • Automatic power-down when deselected
  • CMOS for optimum speed/power
  • Packages offered in a 48-ball FBGA
CY62136CV Description

    The and CY62136CV are high-performance CMOS static RAM organized as 128K words by 16 bits. This device features advanced circuit design to provide ultra-low active current. This is ideal for providing More Battery Life? (MoBL®) in portable applications such as cellular telephones. The device also has an automatic power-down feature that significantly reduces power consumption by 80% when addresses are not toggling. The device can also be put into standby mode reducing power consumption by more than 99% when deselected (/CE HIGH). The input/output pins (I/O0 through I/O15) are placed in a high-impedance state when: deselected (/CE HIGH), outputs are disabled (/OE HIGH), both Byte High Enable and Byte Low Enable are disabled (/BHE, /BLE HIGH), or during a write operation (/CE LOW, and /WE LOW).

    Writing to the device is accomplished by taking Chip Enable (/CE) and Write Enable (/WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is written into the location specified on the address pins (A0 through A16). If Byte High Enable (/BHE) is LOW, then data from I/O pins (I/O8 through I/O15) is written into the location specified on the address pins (A0 through A16).

    Reading from the device is accomplished by taking Chip Enable (/CE) and Output Enable (/OE) LOW while forcing the Write Enable (/WE) HIGH. If Byte Low Enable (/BLE) is LOW, then data from the memory location specified by the address pins will appear on I/O0 to I/O7. If Byte High Enable (/BHE) is LOW, then data from memory will appear on I/O8 to I/O15. See the truth table at the back of this data sheet for a complete description of read and write modes.

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