CY62136CV18LL-55BAI | ||||||||
CY62136CV18LL-55BAI ManufacturerCY62136CV18LL-55BAI DescriptionCY62136CV18LL-55BAI Datasheet (PDF)CY62136CV18LL-55BAI Price & AvailabilityCY62136CV18LL-55BAI Features
CY62136CV18LL-55BAI DescriptionThe CY62136CV18 is a high-performance CMOS static RAM organized as 128K words by 16 bits. This device features advanced circuit design to provide ultra-low active current. This is ideal for providing More Battery Life® (MoBL?) in portable applications such as cellular telephones. The device also has an automatic power-down feature that significantly reduces power consumption by 99% when addresses are not toggling. The device can also be put into standby mode when deselected (/CE HIGH). The input/output pins (I/O0 through I/O15) are placed in a high-impedance state when: deselected (/CE HIGH), outputs are disabled (/OE HIGH), both Byte High Enable and Byte Low Enable are disabled (/BHE, /BLE HIGH), or during a write operation (/CE LOW and /WE LOW). Writing to the device is accomplished by taking Chip Enable (/CE) and Write Enable (/WE) inputs LOW. If Byte Low Enable (/BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is written into the location specified on the address pins (A0 through A16). If Byte High Enable (/BHE) is LOW, then data from I/O pins (I/O8 through I/O15) is written into the location specified on the address pins (A0 through A16). Reading from the device is accomplished by taking Chip Enable (/CE) and Output Enable (/OE) LOW while forcing the Write Enable (/WE) HIGH. If Byte Low Enable (/BLE) is LOW, then data from the memory location specified by the address pins will appear on I/O0 to I/O7. If Byte High Enable (/BHE) is LOW, then data from memory will appear on I/O8 to I/O15. See the Truth Table at the back of this data sheet for a complete description of read and write modes. The CY62136CV18 is available in 48-ball FBGA packaging. CY62136CV18LL-55BAI ParametersProducts Similar to CY62136CV18LL-55BAIKeywords
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