CY62147CV18LL-55BVI

CY62147CV18LL-55BVI Manufacturer

CY62147CV18LL-55BVI Description

CY62147CV18LL-55BVI Datasheet (PDF)

CY62147CV18LL-55BVI Price & Availability

CY62147CV18LL-55BVI Features

• High speed
  • 55 ns and 70 ns availability
• Low voltage range:
  • 1.65V-1.95V
• Pin-compatible w/ CY62147BV18
• Ultra-low active power
  • Typical Active Current: 0.5 mA @ f = 1 MHz
  • Typical Active Current: 2 mA @ f = f_max (70 ns speed)
• Low standby power
• Easy memory expansion with /CE and /OE features
• Automatic power-down when deselected
• CMOS for optimum speed/power

CY62147CV18LL-55BVI Description

The CY62147CV18 is a high-performance CMOS static RAM organized as 256K words by 16 bits. This device features advanced circuit design to provide ultra-low active current. This is ideal for providing More Battery Life? (MoBL^®) in portable applications such as cellular telephones. The device also has an automatic power-down feature that significantly reduces power consumption by 99% when addresses are not toggling. The device can also be put into standby mode when deselected (/CE HIGH or both /BLE and /BHE are HIGH). The input/output pins (I/O₀ through I/O₁₅) are placed in a high-impedance state when: deselected (/CE HIGH), outputs are disabled (/OE HIGH), both Byte High Enable and Byte Low Enable are disabled (/BHE, /BLE HIGH), or during a write operation (/CE LOW and /WE LOW).

Writing to the device is accomplished by taking Chip Enable (/CE) and Write Enable (/WE) inputs LOW. If Byte Low Enable (/BLE) is LOW, then data from I/O pins (I/O₀ through I/O₇), is written into the location specified on the address pins (A₀ through A₁₇). If Byte High Enable (/BHE) is LOW, then data from I/O pins (I/O₈ through I/O₁₅) is written into the location specified on the address pins (A₀ through A₁₇).

Reading from the device is accomplished by taking Chip Enable (/CE) and Output Enable (/OE) LOW while forcing the Write Enable (/WE) HIGH. If Byte Low Enable (/BLE) is LOW, then data from the memory location specified by the address pins will appear on I/O₀ to I/O₇. If Byte High Enable (/BHE) is LOW, then data from memory will appear on I/O₈ to I/O₁₅. See the Truth Table at the back of this data sheet for a complete description of read and write modes.

The CY62147CV18 is available in a 48-ball FBGA package.

CY62147CV18LL-55BVI Parameters

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