CY62158DV30LL-55BVI Datasheet

• Very high speed: 45 ns, 55 ns and 70 ns
  • Wide voltage range: 2.20V ? 3.60V
• Ultra-low active power
  • Typical active current:1.5 mA @ f = 1 MHz
  • Typical active current: 12 mA @ f = fmax
• Ultra-low standby power
• Easy memory expansion with CE1, CE2, and OE features
• Automatic power-down when deselected
• CMOS for optimum speed/power
• Packages offered in a 48-ball BGA, 48-pin TSOPI, and 44-pin TSOPII

The CY62158DV30 is a high-performance CMOS static RAMs organized as 1024K words by 8 bits. This device features advanced circuit design to provide ultra-low active current. This is ideal for providing More Battery Life? (MoBLŽ) in portable applications such as cellular telephones. The device also has an automatic power-down feature that significantly reduces power consumption. The device can be put into standby mode reducing power consumption by 85% when deselected (/CE1 HIGH or CE2 LOW).

Writing to the device is accomplished by taking Chip Enable 1 (/CE1) and Write Enable (/WE) inputs LOW and Chip Enable 2 (CE2) HIGH. Data on the eight I/O pins (I/O0 through I/O7) is then written into the location specified on the address pins (A0 through A19).

Reading from the device is accomplished by taking Chip Enable 1 (/CE1) and Output Enable (/OE) LOW and Chip Enable 2 (CE2) HIGH while forcing Write Enable (/WE) HIGH. Under these conditions, the contents of the memory location specified by the address pins will appear on the I/O pins.

The eight input/output pins (I/O0 through I/O7) are placed in a high-impedance state when the device is deselected (/CE1 LOW and CE2 HIGH), the outputs are disabled (/OE HIGH), or during a write operation (/CE1 LOW and CE2 HIGH and /WE LOW). See the truth table for a complete description of read and write modes.