CY62167DV30LL-70BVI

CY62167DV30LL-70BVI Manufacturer

CY62167DV30LL-70BVI Description

CY62167DV30LL-70BVI Description

CY62167DV30LL-70BVI Datasheet (PDF)

CY62167DV30LL-70BVI Price & Availability

CY62167DV30LL-70BVI Features

• Very high speed: 55 ns
• Wide voltage range: 2.20V ? 3.60V
• Ultra-low active power
  • Typical active current: 2 mA @ f = 1 MHz
  • Typical active current: 15 mA @ f = fmax
• Ultra-low standby power
• Easy memory expansion with /CE1, CE2, and /OE features
• Automatic power-down when deselected
• CMOS for optimum speed/power
• Packages offered in a 48-ball BGA and 48-pin TSOPI

CY62167DV30LL-70BVI Description

The CY62167DV30 is a high-performance CMOS static RAM organized as 1M words by 16 bits. This device features advanced circuit design to provide ultra-low active current.

This is ideal for providing More Battery Life. (MoBL.) in portable applications such as cellular telephones. The device also has an automatic power-down feature that significantly reduces power consumption by 99% when addresses are not toggling. The device can also be put into standby mode when deselected (/CE1 HIGH or CE2 LOW or both /BHE and /BLE are HIGH). The input/output pins (I/O0 through I/O15) are placed in a high-impedance state when: deselected (/CE1HIGH or CE2 LOW), outputs are disabled (/OE HIGH), both Byte High Enable and Byte Low Enable are disabled (/BHE, /BLE HIGH), or during a Write operation (/CE1 LOW, CE2 HIGH and /WE LOW).

Writing to the device is accomplished by taking Chip Enables

(/CE1 LOW and CE2 HIGH) and Write Enable (/WE) input LOW.

If Byte Low Enable (/BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is written into the location specified on the address pins (A0 through A19). If Byte High Enable (/BHE) is LOW, then data from I/O pins (I/O8 through I/O15) is written into the location specified on the address pins (A0 through A19).

CY62167DV30LL-70BVI Parameters

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