CY62168DV30LL-70BVI

CY62168DV30LL-70BVI Manufacturer

CY62168DV30LL-70BVI Description

CY62168DV30LL-70BVI Datasheet (PDF)

CY62168DV30LL-70BVI Price & Availability

CY62168DV30LL-70BVI Features

• Very high speed: 55 ns and 70 ns
• Wide voltage range: 2.2V to 3.6V
• Ultra-low active power
  • Typical active current: 2 mA @ f = 1 MHz
  • Typical active current: 15 mA @ f = fMAX
• Ultra-low standby power
• Easy memory expansion with /CE1, CE2, and /OE features
• Automatic power-down when deselected
• CMOS for optimum speed/power
• Packages offered in a 48-ball FBGA

CY62168DV30LL-70BVI Description

The CY62168DV30 is a high-performance CMOS static RAM organized as 2048K words by eight bits. This device features advanced circuit design to provide ultra-low active current. This is ideal for providing More Battery Life ?(MoBLŽ) in portable applications such as cellular telephones. The device also has an automatic power-down feature that significantly reduces power consumption by 90% when addresses are not toggling. The device can be put into standby mode reducing power consumption by more than 99% when deselected Chip Enable 1 (/CE1) HIGH or Chip Enable 2 (CE2) LOW. The input/output pins (I/O0 through I/O7) are placed in a high-impedance state when: deselected Chip Enable 1 (/CE1) HIGH or Chip Enable 2 (CE2) LOW, outputs are disabled (/OE HIGH), or during a write operation ( Chip Enable 1 (/CE1) LOW and Chip Enable 2 (CE2) HIGH and /WE LOW). Writing to the device is accomplished by taking Chip Enable 1 (/CE1) LOW and Chip Enable 2 (CE2) HIGH and Write Enable (/WE) input LOW. Data on the eight I/O pins (I/O0 through I/O7) is then written into the location specified on the address pins (A0 through A20).

Reading from the device is accomplished by taking Chip Enable 1 (/CE1) LOW and Chip Enable 2 (CE2) HIGH and Output Enable (OE) LOW while forcing the Write Enable (/WE) HIGH. Under these conditions, the contents of the memory location specified by the address pins will appear on the I/O pins. The eight input/output pins (I/O0 through I/O7) are placed in a high-impedance state when the device is deselected(/CE1 LOW and CE2 HIGH), the outputs are disabled (/OE HIGH), or during a write operation (/CE1 LOW and CE2 HIGH and /WE LOW). See the truth table at the back of this data sheet for a complete description of read and write modes.

CY62168DV30LL-70BVI Parameters

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