CY7C006A

CY7C006A Description

CY7C006A Manufacturer

CY7C006A Datasheet (PDF)

CY7C006A Price & Availability

CY7C006A Features

• True dual-ported memory cells which allow simultaneous access of the same memory location
• 16K x 8 organization (CY7C006A)
• 32K x 8 organization (CY7C007A)
• 16K x 9 organization (CY7C016A)
• 32K x 9 organization (CY7C017A)
• 0.35-micron CMOS for optimum speed/power
• High-speed access: 12/15/20 ns
• Low operating power
  • Active: ICC = 180 mA (typical)
  • Standby: ISB3 = 0.05 mA (typical)
• Fully asynchronous operation
• Automatic power-down
• Expandable data bus to 16/18 bits or more using Master/Slave chip select when using more than one device
• On-chip arbitration logic
• Semaphores included to permit software handshaking between ports
• /INT flags for port-to-port communication
• Pin select for Master or Slave
• Commercial temperature range
• Available in 68-pin PLCC (CY7C006A, CY7C007A and CY7C017A), 64-pin TQFP (CY7C006A), and in 80-pin TQFP (CY7C007A and CY7C016A)

CY7C006A Description

The CY7C006A, CY7C007A, CY7C016A, and CY7C017A are low-power CMOS 32K x 8/9 and 16K x 8/9 dual-port static RAMs. Various arbitration schemes are included on the devices to handle situations when multiple processors access the same piece of data. Two ports are provided, permitting independent, asynchronous access for reads and writes to any location in memory. The devices can be utilized as standalone 8/9-bit dual-port static RAMs or multiple devices can be combined in order to function as a 16/18-bit or wider master/slave dual-port static RAM. An M/S pin is provided for implementing 16/18-bit or wider memory applications without the need for separate master and slave devices or additional discrete logic. Application areas include interprocessor/multiprocessor designs, communications status buffering, and dual-port video/graphics memory.

Each port has independent control pins: Chip Enable (/CE), Read or Write Enable (R//W), and Output Enable (/OE). Two flags are provided on each port (/BUSY and /INT). /BUSY signals that the port is trying to access the same location currently being accessed by the other port. The Interrupt flag (/INT) per­mits communication between ports or systems by means of a mail box. The semaphores are used to pass a flag, or token, from one port to the other to indicate that a shared resource is in use. The semaphore logic is comprised of eight shared latches. Only one side can control the latch (semaphore) at any time. Control of a semaphore indicates that a shared re­source is in use. An automatic power-down feature is con­trolled independently on each port by a Chip Select (/CE) pin.

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