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CY7C009V-15AC

CY7C009V-15AC Manufacturer

CY7C009V-15AC Description

CY7C009V-15AC Datasheet (PDF)

CY7C009V-15AC Datasheet

CY7C009V-15AC Price & Availability


Check CY7C009V-15AC Price & Availability at Canics

CY7C009V-15AC Features

  • True Dual-Ported memory cells which allow simultaneous access of the same memory location
  • 64K x 8 organization (CY7C008)
  • 128K x 8 organization (CY7C009)
  • 64K x 9 organization (CY7C018)
  • 128K x 9 organization (CY7C019)
  • 0.35-micron CMOS for optimum speed/power
  • High-speed access: 15/20/25 ns
  • Low operating power
  • Active: ICC = 115 mA (typical)
  • Standby: ISB3 = 10 µA (typical)
  • Fully asynchronous operation
  • Automatic power-down
  • Expandable data bus to 16/18 bits or more using Master/Slave chip select when using more than one device
  • On-chip arbitration logic
  • Semaphores included to permit software handshaking between ports
  • INT flag for port-to-port communication
  • Dual Chip Enables
  • Pin select for Master or Slave
  • Commercial and Industrial Temperature Ranges
  • Available in 100-pin TQFP

CY7C009V-15AC Parameters

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