CY7C017A

CY7C017A Manufacturer

CY7C017A Description

CY7C017A Datasheet (PDF)

CY7C017A Price & Availability

CY7C017A Features

• True dual-ported memory cells which allow simultaneous access of the same memory location
• 16K x 8 organization (CY7C006A)
• 32K x 8 organization (CY7C007A)
• 16K x 9 organization (CY7C016A)
• 32K x 9 organization (CY7C017A)
• 0.35-micron CMOS for optimum speed/power
• High-speed access: 12^[1]/15/20 ns
• Low operating power
  • Active: I_CC = 180 mA (typical)
  • Standby: I_SB3 = 0.05 mA (typical)
• Fully asynchronous operation
• Automatic power-down
• Expandable data bus to 16/18 bits or more using Master/Slave chip select when using more than one device
• On-chip arbitration logic
• Semaphores included to permit software handshaking between ports
• INT flags for port-to-port communication
• Pin select for Master or Slave
• Commercial temperature range
• Available in 68-pin PLCC (CY7C006A, CY7C007A and CY7C017A), 64-pin TQFP (CY7C006A), and in 80-pin TQFP (CY7C007A and CY7C016A)
• Pin-compatible and functionally equivalent to IDT7006 and IDT7007

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