CY7C036A Datasheet

True dual-ported memory cells which allow simultaneous access of the same memory location
16K x 16 organization (CY7C026A)
16K x 18 organization (CY7C036A)
0.35-micron CMOS for optimum speed/power
High-speed access: 12^[1]/15/20 ns
Low operating power
- Active: I_CC = 180 mA (typical)
- Standby: I_SB3 = 0.05 mA (typical)
Fully asynchronous operation
Automatic power-down
Expandable data bus to 32/36 bits or more using Master/Slave chip select when using more than one device
On-chip arbitration logic
Semaphores included to permit software handshaking between ports
INT flags for port-to-port communication
Separate upper-byte and lower-byte control
Pin select for Master or Slave
Commercial and Industrial temperature ranges
Available in 100-Pin TQFP
Pin-compatible and functionally equivalent to IDT70261

CY7C036A