CY7C057V Datasheet

True dual-ported memory cells which allow simult aneous access of the same memory location
16K x 36 organization (CY7C056V)
32K x 36 organization (CY7C057V)
0.25-micron CMOS for optimum speed/power
High-speed access: 12/15/20 ns
Low operating power
- Active: I_CC = 250 mA (typical)
- Standby: I_SB3 = 10 渙 (typical)
Fully asynchronous operation
Automatic power-down
Expandable data bus to 72 bits or more using Master/Slave Chip Select when using more than one device
On-Chip arbitration logic
Semaphores included to permit software handshaking between ports
NT flag for port-to-port communication
Byte Select on Left Port
Bus Matching on Right Port
Depth Expansion via dual chip enables
Pin select for Master or Slave
Commercial and Industrial Temperature Ranges
Compact package
- 144-Pin TQFP (20 x 20 x 1.4 mm)
- 172-Ball BGA (1.0-mm pitch) (15 x 15 x.51 mm)

CY7C057V