CY7C0853V

CY7C0853V Manufacturer

CY7C0853V Description

CY7C0853V Datasheet (PDF)

CY7C0853V Price & Availability

CY7C0853V Features

• True dual-ported memory cells that allow simultaneous access of the same memory location
• Synchronous pipelined
• Organization
  • 256K × 36
• 0.18-micron CMOS for optimum speed and power
• High-speed clock to data access: 5.0 ns (max.)
• 3.3V low operating power
  • Active = 270 mA (typical)
• Interrupt flags for message passing
• Global master reset
• Separate byte enables on both ports
• Commercial and industrial temperature ranges
• IEEE 1149.1-compatible JTAG boundary scan
• 172-ball BGA (1 mm pitch) (15 mm × 15 mm)
• FLEx36? devices are pin footprint upgradeable from 2M to 4M to 9M

CY7C0853V Description

The CY7C0853V is a 9M pipelined, synchronous, true dual-port static RAM that is high-speed, low-power 3.3V CMOS. Two ports are provided, permitting independent, simultaneous access for Reads from any location in memory. The result of writing to the same location by more than one port at the same time is undefined. Registers on control, address, and data lines allow for minimal set-up and hold time.

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