CY7C1011CV33-12AC Datasheet

• Pin equivalent to CY7C1011BV33
• High speed
  • t_AA = 10 ns
• Low active power
  • 360 mW (max.)
• Data Retention at 2.0
• Automatic power-down when deselected
• Independent control of upper and lower bits
• Easy memory expansion with /CE and /OE features
• Available in 44-pin TSOP II, 44-pin TQFP, and 48-ball VFBGA

The CY7C1011CV33 is a high-performance CMOS Static RAM organized as 131,072 words by 16 bits.

Writing to the device is accomplished by taking Chip Enable (/CE) and Write Enable (/WE) inputs LOW. If Byte Low Enable (/BLE) is LOW, then data from I/O pins (I/O₀ through I/O₇), is written into the location specified on the address pins (A₀ through A₁₆). If Byte High Enable (/BHE) is LOW, then data from I/O pins (I/O₈ through I/O₁₅) is written into the location specified on the address pins (A₀ through A₁₆).

Reading from the device is accomplished by taking Chip Enable (/CE) and Output Enable (/OE) LOW while forcing the Write Enable (/WE) HIGH. If Byte Low Enable (/BLE) is LOW, then data from the memory location specified by the address pins will appear on I/O₀ to I/O₇. If Byte High Enable (/BHE) is LOW, then data from memory will appear on I/O₈ to I/O₁₅. See the truth table at the back of this data sheet for a complete description of read and write modes.

The input/output pins (I/O₀ through I/O₁₅) are placed in a high-impedance state when the device is deselected (/CE HIGH), the outputs are disabled (/OE HIGH), the /BHE and /BLE are disabled (/BHE, /BLE HIGH), or during a write operation (/CE LOW, and /WE LOW).

The CY7C1011CV33 is available in a standard 44-pin TSOP II package with center power and ground pinout, a 44-pin Thin Plastic Quad Flatpack (TQFP), as well as a 48-ball fine-pitch ball grid array (VFBGA) package.