CY7C1018CV33
CY7C1018CV33 Description
Memory : Async SRAMs
CY7C1018CV33 Vendor
Cypress
CY7C1018CV33 Categories
CY7C1018CV33 Features
  • Pin- and function-compatible with CY7C1018BV33
  • High speed
    • tAA = 8, 10, 12, 15 ns
  • CMOS for optimum speed/power
  • Center power/ground pinout
  • Data retention at 2.0V
  • Automatic power-down when deselected
  • Easy memory expansion with /CE and /OE options
  • Available in 300-mil-wide 32-pin SOJ
CY7C1018CV33 Description

    The CY7C1018CV33 is a high-performance CMOS static RAM organized as 131,072 words by 8 bits. Easy memory expansion is provided by an active LOW Chip Enable (/CE), an active LOW Output Enable (/OE), and three-state drivers. This device has an automatic power-down feature that significantly reduces power consumption when deselected.

    Writing to the device is accomplished by taking Chip Enable (/CE) and Write Enable (/WE) inputs LOW. Data on the eight I/O pins (I/O0 through I/O7) is then written into the location specified on the address pins (A0 through A16).

    Reading from the device is accomplished by taking Chip Enable (/CE) and Output Enable (/OE) LOW while forcing Write Enable (/WE) HIGH. Under these conditions, the contents of the memory location specified by the address pins will appear on the I/O pins.

    The eight input/output pins (I/O0 through I/O7) are placed in a high-impedance state when the device is deselected (/CE HIGH), the outputs are disabled (/OE HIGH), or during a write operation (/CE LOW, and /WE LOW).

    The CY7C1018CV33 is available in a standard 300-mil-wide SOJ.

CY7C1018CV33 Datasheet and Application Notes
Products related to CY7C1018CV33
CY7C1018CV33-12VI   CY7C1018CV33-12VC   CY7C1018CV33-10VC   CY7C1018CV33-15VC   

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