CY7C1019CV33-12VI

CY7C1019CV33-12VI Manufacturer

CY7C1019CV33-12VI Description

CY7C1019CV33-12VI Datasheet (PDF)

CY7C1019CV33-12VI Price & Availability

CY7C1019CV33-12VI Features

• Pin and function compatible with CY7C1019BV33
• High speed
  • t_AA = 8, 10, 12, 15 ns
• CMOS for optimum speed/power
• Data Retention at 2.0V
• Center power/ground pinout
• Automatic power-down when deselected
• Easy memory expansion with /CE  and /OE options
• Available in 32-pin TSOP II and 400-mil SOJ package

CY7C1019CV33-12VI Description

The CY7C1019CV33 is a high-performance CMOS static RAM organized as 131,072 words by 8 bits. Easy memory expansion is provided by an active LOW Chip Enable (/CE), an active LOW Output Enable (/OE), and three-state drivers. This device has an automatic power-down feature that significantly reduces power consumption when deselected.

Writing to the device is accomplished by taking Chip Enable (/CE) and Write Enable (/WE) inputs LOW. Data on the eight I/O pins (I/O₀ through I/O₇) is then written into the location specified on the address pins (A₀ through A₁₆).

Reading from the device is accomplished by taking Chip Enable (/CE) and Output Enable (/OE) LOW while forcing Write Enable (/WE) HIGH. Under these conditions, the contents of the memory location specified by the address pins will appear on the I/O pins.

The eight input/output pins (I/O₀ through I/O₇) are placed in a high-impedance state when the device is deselected (/CE HIGH), the outputs are disabled (/OE HIGH), or during a write operation (/CE LOW, and /WE LOW).

The CY7C1019CV33 is available in a standard 32-pin TSOP II and 400-mil-wide SOJ.

CY7C1019CV33-12VI Parameters

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