CY7C1041CV33-12ZC

CY7C1041CV33-12ZC Manufacturer

CY7C1041CV33-12ZC Description

CY7C1041CV33-12ZC Description

CY7C1041CV33-12ZC Datasheet (PDF)

CY7C1041CV33-12ZC Price & Availability

CY7C1041CV33-12ZC Features

• Pin equivalent to CY7C1041BV33
• High speed
  • t_AA = 10 ns
• Low active power
  • 324 mW (max.)
• 2.0V data retention
• Automatic power-down when deselected
• TTL-compatible inputs and outputs
• Easy memory expansion with /CE and /OE features

CY7C1041CV33-12ZC Description

The CY7C1041CV33 is a high-performance CMOS Static RAM organized as 262,144 words by 16 bits.

Writing to the device is accomplished by taking Chip Enable (/CE) and Write Enable (/WE) inputs LOW. If Byte LOW Enable (/BLE) is LOW, then data from I/O pins (I/O₀?I/O₇), is written into the location specified on the address pins (A₀?A₁₇). If Byte HIGH Enable (/BHE) is LOW, then data from I/O pins (I/O₈?I/O₁₅) is written into the location specified on the address pins (A₀?A₁₇).

Reading from the device is accomplished by taking Chip Enable (/CE) and Output Enable (/OE) LOW while forcing the Write Enable (/WE) HIGH. If Byte LOW Enable (/BLE) is LOW, then data from the memory location specified by the address pins will appear on I/O₀ ? I/O₇. If Byte HIGH Enable (/BHE) is LOW, then data from memory will appear on I/O₈ to I/O₁₅. See the truth table at the back of this data sheet for a complete description of Read and Write modes.

The input/output pins (I/O₀?I/O₁₅) are placed in a high-impedance state when the device is deselected (/CE HIGH), the outputs are disabled (/OE HIGH), the /BHE and /BLE are disabled (/BHE, /BLE HIGH), or during a Write operation (/CE LOW, and /WE LOW).

The CY7C1041CV33 is available in a standard 44-pin 400-mil-wide body width SOJ and 44-pin TSOP II package with center power and ground (revolutionary) pinout, as well as a 48-ball fine-pitch ball grid array (FBGA) package.

CY7C1041CV33-12ZC Parameters

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