The CY7C1061AV25 is a high-performance CMOS Static RAM organized as 1,048,576 words by 16 bits. Writing to the device is accomplished by enabling the chip (/CE1 LOW and CE2 HIGH) while forcing the Write Enable (/WE) input LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is written into the location specified on the address pins (A0 through A19). If Byte High Enable (/BHE) is LOW, then data from I/O pins (I/O8 through I/O15) is written into the location specified on the address pins (A0 through A19). Reading from the device is accomplished by enabling the chip by taking /CE1 LOW and CE2 HIGH while forcing the Output Enable (/OE) LOW and the Write Enable (/WE) HIGH. If Byte Low Enable (/BLE) is LOW, then data from the memory location specified by the address pins will appear on I/O0 to I/O7. If Byte High Enable (/BHE) is LOW, then data from memory will appear on I/O8 to I/O15. See the truth table at the back of this data sheet for a complete description of Read and Write modes. The input/output pins (I/O0 through I/O15) are placed in a high-impedance state when the device is deselected (/CE1 HIGH/CE2 LOW), the outputs are disabled (OE HIGH), the BHE and BLE are disabled (/BHE, /BLE HIGH), or during a Write operation (/CE1 LOW, CE2 HIGH, and /WE LOW). The CY7C1061AV25 is available in a 54-pin TSOP II package with center power and ground (revolutionary) pinout, and a 48-ball fine-pitch ball grid array (FBGA) package.
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