CY7C1061AV33-10ZC Datasheet

• High speed
  • t_AA = 8, 10, 12 ns
• Low active power
  • 1080 mW (max.)
• Operating voltages of 3.3 ħ 0.3V
• 2.0V data retention
• Automatic power-down when deselected
• TTL-compatible inputs and outputs
• Easy memory expansion with CE₁ and CE₂ features

The CY7C1061AV33 is a high-performance CMOS Static RAM organized as 1,048,576 words by 16 bits.

Writing to the device is accomplished by enabling the chip (/CE₁ LOW and CE₂ HIGH) while forcing the Write Enable (/WE) input LOW. If Byte Low Enable (/BLE) is LOW, then data from I/O pins (I/O₀ through I/O₇), is written into the location specified on the address pins (A₀ through A₁₉). If Byte High Enable (/BHE) is LOW, then data from I/O pins (I/O₈ through I/O₁₅) is written into the location specified on the address pins (A₀ through A₁₉).

Reading from the device is accomplished by enabling the chip by taking /CE₁ LOW and CE₂ HIGH while forcing the Output Enable (/OE) LOW and the Write Enable (/WE) HIGH. If Byte Low Enable (/BLE) is LOW, then data from the memory location specified by the address pins will appear on I/O₀ to I/O₇. If Byte High Enable (/BHE) is LOW, then data from memory will appear on I/O₈ to I/O₁₅. See the truth table at the back of this data sheet for a complete description of Read and Write modes.

The input/output pins (I/O₀ through I/O₁₅) are placed in a high-impedance state when the device is deselected (/CE₁ HIGH/CE₂ LOW), the outputs are disabled (/OE HIGH), the BHE and BLE are disabled /(BHE, BLE HIGH), or during a Write operation (/CE₁ LOW, CE₂ HIGH, and /WE LOW).

The CY7C1061AV33 is available in a 54-pin TSOP II package with center power and ground (revolutionary) pinout, and a 48-ball fine-pitch ball grid array (FBGA) package.