CY7C1231F

CY7C1231F Description

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CY7C1231F Manufacturer

CY7C1231F Datasheet (PDF)

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CY7C1231F Features

• Can support up to 117-MHz bus operations with zero wait states
  • Data is transferred on every clock
• Pin compatible and functionally equivalent to ZBT? devices
• Internally self-timed output buffer control to eliminate the need to use /OE
• Registered inputs for flow-through operation
• Byte Write capability
• 128K x 18 common I/O architecture
• Single 3.3V power supply
• Fast clock-to-output times
  • 7.5 ns (for 117-MHz device)
  • 8.5 ns (for 100-MHz device)
• Clock Enable (/CEN) pin to suspend operation
• Synchronous self-timed writes
• Asynchronous Output Enable
• JEDEC-standard 100 TQFP package
• Burst Capability?linear or interleaved burst order
• Low standby power

CY7C1231F Description

The CY7C1231F is a 3.3V, 128K x 18 Synchronous Flow-through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1231F is equipped with the advanced No Bus Latency? (NoBL?) logic required to enable consecutive Read/Write operations with data being transferred on every clock cycle. This feature dramatically improves the throughput of data through the SRAM, especially in systems that require frequent Write-Read transitions.

All synchronous inputs pass through input registers controlled by the rising edge of the clock. The clock input is qualified by the Clock Enable (/CEN) signal, which when deasserted suspends operation and extends the previous clock cycle. Maximum access delay from the clock rise is 7.5 ns (117-MHz device).

Write operations are controlled by the two Byte Write Select (/BW[A:B]) and a Write Enable (/WE) input. All writes are conducted with on-chip synchronous self-timed write circuitry.

Three synchronous Chip Enables (/CE1, CE2, /CE3) and an asynchronous Output Enable (/OE) provide for easy bank selection and output three-state control. In order to avoid bus contention, the output drivers are synchronously three-stated during the data portion of a write sequence.

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