CY7C1306AV25-100BZC

CY7C1306AV25-100BZC Description

CY7C1306AV25-100BZC Manufacturer

CY7C1306AV25-100BZC Datasheet (PDF)

CY7C1306AV25-100BZC Price & Availability

CY7C1306AV25-100BZC Features

• Separate independent Read and Write data ports
  • Supports concurrent transactions
• 167-MHz Clock for high bandwidth
  • 2.5 ns Clock-to-Valid access time
• 2-Word Burst on all accesses
• Double Data Rate (DDR) interfaces on both Read and Write Ports (data transferred at 333 MHz) @167 MHz
• Two input clocks (K and /K) for precise DDR timing
  • SRAM uses rising edges only
• Two output clocks (C and /C) account for clock skew and flight time mismatching
• Single multiplexed address input bus latches address inputs for both Read and Write ports
• Separate Port Selects for depth expansion
• Synchronous internally self-timed writes
• 2.5V core power supply with HSTL Inputs and Outputs
• 13 x 15 x 1.4 mm 1.0-mm pitch fBGA package, 165 ball (11x15 matrix) Variable drive HSTL output buffers
• Expanded HSTL output voltage (1.4V?1.9V)
• JTAG Interface
• Variable Impedance HSTL

CY7C1306AV25-100BZC Description

The CY7C1303AV25 and CY7C1306AV25 are 2.5V Synchronous Pipelined SRAMs equipped with QDR? architecture. QDR architecture consists of two separate ports to access the memory array. The Read port has dedicated Data Outputs to support Read operations and the Write Port has dedicated Data inputs to support Write operations. Access to each port is accomplished through a common address bus. The Read address is latched on the rising edge of the K clock and the Write address is latched on the rising edge of K clock. QDR has separate data inputs and data outputs to completely eliminate the need to ?turn-around? the data bus required with common I/O devices. Accesses to the CY7C1303AV25/CY7C1306AV25 Read and Write ports are completely independent of one another. All accesses are initiated synchronously on the rising edge of the positive input clock (K). In order to maximize data throughput, both Read and Write ports are equipped with Double Data Rate (DDR) interfaces. Therefore, data can be transferred into the device on

every rising edge of both input clocks (K and /K) and out of the device on every rising edge of the output clock (C and /C, or K and /K when in single clock mode) thereby maximizing performance while simplifying system design. Each address location is associated with two 18-bit words (CY7C1303AV25) or two 36-bit words (CY7C1306AV25) that burst sequentially into or out of the device.

Depth expansion is accomplished with a Port Select input for each port. Each Port Selects allow each port to operate independently.

All synchronous inputs pass through input registers controlled by the K or /K input clocks. All data outputs pass through output registers controlled by the C or C input clocks. Writes are conducted with on-chip synchronous self-timed write circuitry.

CY7C1306AV25-100BZC Parameters

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