CY7C1352G

CY7C1352G Manufacturer

CY7C1352G Description

CY7C1352G Datasheet (PDF)

CY7C1352G Price & Availability

CY7C1352G Features

• Pin compatible and functionally equivalent to ZBT? devices
• Internally self-timed output buffer control to eliminate the need to use OE
• Byte Write capability
• 256K x 18 common I/O architecture
• Single 3.3V power supply
• 2.5V / 3.3V I/O Operation
• Fast clock-to-output times
• 2.6 ns (for 250-MHz device)
• 2.6 ns (for 225-MHz device)
• 2.8 ns (for 200-MHz device)
• 3.5 ns (for 166-MHz device)
• 4.0 ns (for 133-MHz device)
• 4.5 ns (for 100-MHz device)
• Clock Enable (/CEN) pin to suspend operation
• Synchronous self-timed writes
• Asynchronous output enable (/OE)
• JEDEC-standard 100 TQFP package
• Burst Capability?linear or interleaved burst order
• ZZ? Sleep Mode Option and Stop Clock option

CY7C1352G Description

The CY7C1352G is a 3.3V, 256K x 18 synchronous-pipelined Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1352G is equipped with the advanced No Bus Latency? (NoBL?) logic required to enable consecutive Read/Write operations with data being transferred on every clock cycle. This feature dramatically improves the throughput of the SRAM, especially in systems that require frequent Write/Read transitions.

All synchronous inputs pass through input registers controlled by the rising edge of the clock. All data outputs pass through output registers controlled by the rising edge of the clock. The clock input is qualified by the Clock Enable (/CEN) signal, which, when deasserted, suspends operation and extends the previous clock cycle. Maximum access delay from the clock rise is 2.6 ns (250-MHz device).

Write operations are controlled by the two Byte Write Select (BW[A:B]) and a Write Enable (/WE) input. All writes are conducted with on-chip synchronous self-timed write circuitry.