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CY7C1354BV25-200BZC

CY7C1354BV25-200BZC Manufacturer

Cypress

CY7C1354BV25-200BZC Description

256K x 36/512K x 18 Pipelined SRAM with NoBL(TM) Architecture

CY7C1354BV25-200BZC Datasheet (PDF)

CY7C1354BV25-200BZC Datasheet

CY7C1354BV25-200BZC Price & Availability


Check CY7C1354BV25-200BZC Price & Availability at Canics

CY7C1354BV25-200BZC Features

  • Pin-compatible and functionally equivalent to ZBT?
  • Supports 225-MHz bus operations with zero wait states
    • Available speed grades are 225, 200 and 166 MHz
  • Internally self-timed output buffer control to eliminate the need to use asynchronous OE
  • Fully registered (inputs and outputs) for pipelined operation
  • Byte Write capability
  • Single 2.5V power supply
  • Fast clock-to-output times
    • 2.8 ns (for 225-MHz device)
    • 3.2ns (for 200-MHz device)
    • 3.5 ns (for 166-MHz device)
  • Clock Enable (CEN) pin to suspend operation
  • Synchronous self-timed writes
  • Available in 100 TQFP, 119 BGA, and 165 fBGA packages
  • IEEE 1149.1 JTAG Boundary Scan
  • Burst capability?linear or interleaved burst order
  • ?ZZ? Sleep Mode option and Stop Clock option

CY7C1354BV25-200BZC Parameters

Vcc (V)2.5
ArchitecturePipeline
Density9Mb
Organization256Kb x36
100-999 qty $14.90
CommentsProduction
Vccq (V)2.5
Select parameters and click to see components with these parameters.

Products Similar to CY7C1354BV25-200BZC

CY7C1354BV25, CY7C1354BV25-166AC, CY7C1354BV25-166AXC, CY7C1354BV25-166BGC, CY7C1354BV25-166BZC

 
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