| CY7C1354BV25-200BZC Description |
| 256K x 36/512K x 18 Pipelined SRAM with NoBL(TM) Architecture |
| CY7C1354BV25-200BZC Vendor |
| Cypress |
| CY7C1354BV25-200BZC Features |
- Pin-compatible and functionally equivalent to ZBT™
- Supports 225-MHz bus operations with zero wait states
- Available speed grades are 225, 200 and 166 MHz
- Internally self-timed output buffer control to eliminate the need to use asynchronous OE
- Fully registered (inputs and outputs) for pipelined operation
- Byte Write capability
- Single 2.5V power supply
- Fast clock-to-output times
- 2.8 ns (for 225-MHz device)
- 3.2ns (for 200-MHz device)
- 3.5 ns (for 166-MHz device)
- Clock Enable (CEN) pin to suspend operation
- Synchronous self-timed writes
- Available in 100 TQFP, 119 BGA, and 165 fBGA packages
- IEEE 1149.1 JTAG Boundary Scan
- Burst capability—linear or interleaved burst order
- “ZZ” Sleep Mode option and Stop Clock option
|
| CY7C1354BV25-200BZC Datasheet and Application Notes |
|
| Parameter | Value |
| 100-999 qty | $14.90 |
| Architecture | Pipeline |
| Density | 9Mb |
| Organization | 256kb x36 |
| Vcc (V) | 2.5 |
| Vccq (V) | 2.5 |
| Comments | Production |
| Products related to CY7C1354BV25-200BZC |
CY7C1356BV25-200AC CY7C1354BV25-166AXC CY7C1354BV25-166BZC CY7C1354BV25-166BGC
CY7C1354BV25-166AC CY7C1356BV25 CY7C1356BV25-166AXC CY7C1356BV25-166AC
CY7C1354BV25 CY7C1354BV25-200BGC CY7C1354BV25-200AC |