The CY7C1355B/CY7C1357B is a 3.3V, 256K x 36/ 512K x 18 Synchronous Flow-through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1355B/CY7C1357B is equipped with the advanced No Bus Latency (NoBL) logic required to enable consecutive Read/Write operations with data being transferred on every clock cycle. This feature dramatically improves the throughput of data through the SRAM, especially in systems that require frequent Write-Read transitions.

All synchronous inputs pass through input registers controlled by the rising edge of the clock. The clock input is qualified by the Clock Enable (/CEN) signal, which when deasserted suspends operation and extends the previous clock cycle. Maximum access delay from the clock rise is 6.5 ns (133-MHz device).

Write operations are controlled by the two or four Byte Write Select (/BWX) and a Write Enable (/WE) input. All writes are conducted with on-chip synchronous self-timed write circuitry. Three synchronous Chip Enables (/CE1, CE2, /CE3) and an asynchronous Output Enable (/OE) provide for easy bank selection and output three-state control. In order to avoid bus contention, the output drivers are synchronously three-stated during the data portion of a write sequence.