The CY7C1355B and CY7C1357B SRAMs are flow-through synchronous SRAMs designed to eliminate dead cycles when transitions from READ to WRITE or vice versa. These SRAMs are optimized for 100 percent bus utilization with the No Bus Latency (NoBL) architecture. They integrate 262,144 x 36 and 524,288 x 18 SRAM cells, respectively, with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. These employ high-speed, low power CMOS designs using advanced triple-layer polysilicon, double-layer metal technology. Each memory cell consists of Six transistors.

All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). The synchronous inputs include all addresses, all data inputs, depth-expansion Chip Enables (/CE, CE₂, and /CE₃), Cycle Start Input (ADV//LD), Clock Enable (/CEN), Byte Write Enables (/BWa, /BWb, /BWc, and /BWd), and read-write control (R//W). /BWc and /BWd apply to CY7C1355B only.

There are three Chip Enable pins (/CE, CE₂, /CE₃) that allow the user to deselect the device when desired. If any one of these three are not active when ADV//LD is LOW, no new memory operation can be initiated and any burst cycle in progress is stopped. However, any pending data transfers (read or write) will be completed. The data bus will be in high-impedance state one cycle after chip is deselected or a write cycle is initiated.

The CY7C1355B and CY7C1357B have an on-chip two-bit burst counter. In the burst mode, the CY7C1355B and CY7C1357B provide up to four cycles of data for a single address presented to the SRAM. The order of the burst sequence is defined by the MODE input pin. The MODE pin selects between linear and interleaved burst sequence. The ADV//LD signal is used to load a new external address (ADV//LD = LOW) or increment the internal burst counter (ADV//LD = HIGH).