CY7C1358A

CY7C1358A Manufacturer

CY7C1358A Description

CY7C1358A Price & Availability

CY7C1358A Features

• Fast match times: 4.5, 5.0, 6.0, and 7.0 ns
• Fast clock speed: 133, 100, 83, and 75 MHz
• Fast OE access times: 4.5 ns and 5.0 ns
• Pipelined data comparator
• Data input register load control by DEN
• 3.3V ?5% and +10% power supply
• 5V tolerant inputs except I/Os
• Clamp diodes to V SS at all inputs and outputs
• Common data inputs and data outputs
• Two chip enables for depth expansion
• Address, data, and control registers
• Internally self-timed Write cycle
• Automatic power-down for portable applications
• Low profile 100-pin TQFP package

CY7C1358A Description

The Cypress Synchronous SRAM family employs high-speed, low-power CMOS designs using advanced triple-layer polysilicon, double-layer metal technology. Each memory cell consistsof four transistors and two high valued resistors.

The GVT7164T18 SRAM integrates 65,536 x 18 SRAM cells with advanced synchronous peripheral circuitry and a 18-bit comparator for tag compare operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). The synchronous inputs include all addresses, all data inputs, depth-expansion Chip Enables (CE and CE1), Write Enable (WE), and Data Input Enable (DEN).

Asynchronous inputs include the Output Enable (OE) and the Match Output Enable (MOE). The Data Outputs (Q) and Match Output (MATCH), enabled by OE and MOE respectively, are also asynchronous.

Data inputs are registered with Data Input Enable (DEN) and Chip Enable pins (CE, CE1). The outputs of the data input registers are compared with data in the memory array and a match signal is generated. The match output is gated into a pipeline register and released to the match output pin at the next rising edge of Clock (CLK).

The GVT7164T18 operates from a +3.3V power supply. All inputs and outputs are LVTTL compatible. The device is ideally suited for address tag RAM for up to 2 MB secondary cache.