CY7C136-15JC

CY7C136-15JC Manufacturer

CY7C136-15JC Description

CY7C136-15JC Datasheet (PDF)

CY7C136-15JC Price & Availability

CY7C136-15JC Features

• True Dual-Ported memory cells which allow simulta­neous reads of the same memory location
• 2K x 8 organization
• 0.65-micron CMOS for optimum speed/power
• High-speed access: 15 ns
• Low operating power: ICC = 110 mA (max.)
• Fully asynchronous operation
• Automatic power-down
• Master CY7C132/CY7C136 easily expands data bus width to 16 or more bits using slave C7C142/CY7C146
• /BUSY output flag on CY7C132/CY7C136; /BUSY input on CY7C142/CY7C146
• /INT flag for port-to-port communication (52-pin PLCC/PQFP versions)
• Available in 48-pin DIP (CY7C132/142), 52-pin PLCC and 52-pin TQFP (CY7C136/146)

CY7C136-15JC Description

The CY7C132/CY7C136/CY7C142 and CY7C146 are high-speed CMOS 2K by 8 dual-port static RAMs. Two ports are provided to permit independent access to any location in memory. The CY7C132/ CY7C136 can be utilized as either a standalone 8-bit dual-port static RAM or as a MASTER dual-port RAM in conjunction with the CY7C142/CY7C146 SLAVE dual-port device in systems requiring 16-bit or greater word widths. It is the solution to applications requiring shared or buffered data such as cache memory for DSP, bit-slice, or multiprocessor designs.

Each port has independent control pins; chip enable (/CE), write enable (R//W), and output enable (/OE). /BUSY flags are provided on each port. In addition, an interrupt flag (/INT) is provided on each port of the 52-pin PLCC version. /BUSY signals that the port is trying to access the same location currently being accessed by the other port. On the PLCC version, /INT is an interrupt flag indicating that data has been placed in a unique location (7FF for the left port and 7FE for the right port).

CY7C136-15JC Parameters

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