The Cypress Synchronous Burst SRAM family employs high-speed, low-power CMOS designs using advanced triple-layer polysilicon, double-layer metal technology. Each memory cell consists of four transistors and two high-valued resistors.
The CY7C1360A and CY7C1362A SRAMs integrate 262,144 × 36 and 524,288 × 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). The synchronous inputs include all addresses, all data inputs, address-pipelining Chip Enable (/CE), depth-expansion Chip Enables (CE2 and /CE3), burst control inputs (/ADSC, /ADSP, and /ADV), Write Enables (/BWa, /BWb, /BWc, /BWd, and /BWE), and global Write (/GW). However, the CE3 chip enable input is only available for the TA package version.
Asynchronous inputs include the Output Enable (/OE) and burst mode control (MODE). The data outputs (Q), enabled by /OE, are also asynchronous.
Addresses and chip enables are registered with either Address Status Processor (/ADSP) or Address Status Controller (/ADSC) input pins. Subsequent burst addresses can be internally generated as controlled by the Burst Advance Pin (/ADV).
Address, data inputs, and Write controls are registered on-chip to initiate self-timed Write cycle. Write cycles can be one to four bytes wide as controlled by the Write control inputs. Individual byte Write allows individual byte to be written. /BWa controls DQa. /BWb controls DQb. /BWc controls DQc. /BWd controls DQd. /BWa, /BWb, /BWc, and /BWd can be active only with /BWE being LOW. /GW being LOW causes all bytes to be written. The x18 version only has 18 data inputs/outputs (DQa and DQb) along with /BWa and /BWb (no /BWc, /BWd, DQc, and DQd).
For the BGA and TQFP AJ package versions, four pins are used to implement JTAG test capabilities: Test Mode Select (TMS), Test Data-In (TDI), Test Clock (TCK), and Tes