CY7C1363B-117BGC

CY7C1363B-117BGC Manufacturer

CY7C1363B-117BGC Description

CY7C1363B-117BGC Datasheet (PDF)

CY7C1363B-117BGC Price & Availability

CY7C1363B-117BGC Features

• Supports 133-MHz bus operations
• 256K X 36/512K X 18 common I/O
• 3.3V ?5% and +10% core power supply (VDD)
• 2.5V or 3.3V I/O supply (VDDQ)
• Fast clock-to-output times
  • 6.5 ns (133-MHz version)
  • 7.5 ns (117-MHz version)
  • 8.5 ns (100-MHz version)
• Provide high-performance 2-1-1-1 access rate
• User-selectable burst counter supporting IntelŪ PentiumŪ interleaved or linear burst sequences
• Separate processor and controller address strobes
• Synchronous self-timed write
• Asynchronous output enable
• Offered in JEDEC-standard 100-pin TQFP, 119-ball BGA and 165-ball fBGA packages
  • Both 2 and 3 Chip Enable Options for TQFP
• JTAG boundary scan for BGA and fBGA packages
• ?ZZ? Sleep Mode option

CY7C1363B-117BGC Description

The CY7C1361B/CY7C1363B is a 3.3V, 256K x 36 and 512K x 18 Synchronous Flow through SRAMs, respectively designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133-MHz version). A 2-bit on-chip counter captures the first address in a burst and increments the address automatically for the rest of the burst access. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). The synchronous inputs include all addresses, all data inputs, address-pipelining Chip Enable (/CE1), depth-expansion Chip Enables (CE2 and /CE3), Burst Control inputs (/ADSC, /ADSP, and /ADV), Write Enables (/BWX, and /BWE), and Global Write (/GW). Asynchronous inputs include the Output Enable (/OE) and the ZZ pin.

The CY7C1361B/CY7C1363B allows either interleaved or linear burst sequences, selected by the MODE input pin. A HIGH selects an interleaved burst sequence, while a LOW selects a linear burst sequence. Burst accesses can be initiated with the Processor Address Strobe (/ADSP) or the cache Controller Address Strobe (/ADSC) inputs. Address advancement is controlled by the Address Advancement (/ADV) input.

Addresses and chip enables are registered at rising edge of clock when either Address Strobe Processor (/ADSP) or Address Strobe Controller (/ADSC) are active. Subsequent burst addresses can be internally generated as controlled by the Advance pin (/ADV).

CY7C1363B-117BGC Parameters

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