CY7C1381C

CY7C1381C Description

CY7C1381C Categories

CY7C1381C Manufacturer

CY7C1381C Datasheet (PDF)

CY7C1381C Price & Availability

CY7C1381C Features

• Supports 133-MHz bus operations
• 512K X 36/1M X 18 common I/O
• 3.3V ?5% and +10% core power supply (VDD )
• 2.5V or 3.3V I/O supply (VDDQ )
• Fast clock-to-output times
  • 6.5 ns (133-MHz version)
  • 7.5 ns (117-MHz version)
  • 8.5 ns (100-MHz version)
• Provide high-performance 2-1-1-1 access rate
• User-selectable burst counter supporting IntelŪ PentiumŪ interleaved or linear burst sequences
• Separate processor and controller address strobes
• Synchronous self-timed write
• Asynchronous output enable
• Offered in JEDEC-standard 100-pin TQFP ,119-ball BGA and 165-ball fBGA packages
• JTAG boundary scan for BGA and fBGA packages
• ?ZZ? Sleep Mode option

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