The CY7C1381CV25/CY7C1383CV25 is a 2.5V, 512K x 36 and 1M x 18 Synchronous Flow through SRAMs, respectively designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133-MHz version). A 2-bit on-chip counter captures the first address in a burst and increments the address automatically for the rest of the burst access. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). The synchronous inputs include all addresses, all data inputs, address-pipelining Chip Enable (/CE1), depth-expansion Chip Enables (CE2 and /CE3), Burst Control inputs (/ADSC, /ADSP, and /ADV), Write Enables (/BWx, and /BWE), and Global Write (/GW). Asynchronous inputs include the Output Enable (/OE) and the ZZ pin.

The CY7C1381CV25/CY7C1383CV25 allows either interleaved or linear burst sequences, selected by the MODE input pin. A HIGH selects an interleaved burst sequence, while a LOW selects a linear burst sequence. Burst accesses can be initiated with the Processor Address Strobe (/ADSP) or the cache Controller Address Strobe (/ADSC) inputs. Address advancement is controlled by the Address Advancement (/ADV) input.

Addresses and chip enables are registered at rising edge of clock when either Address Strobe Processor (/ADSP) or Address Strobe Controller (/ADSC) are active. Subsequent burst addresses can be internally generated as controlled by the Advance pin (/ADV).

The CY7C1381CV25/CY7C1383CV25 operates from a +2.5V core power supply. All outputs also operate with a +2.5 supply. All inputs and outputs are JEDEC-standard JESD8-5-compatible.