CY7C1444V33 Datasheet - 1M x 36/2M x 18 Pipelined DCD SRAM

CY7C1444V33 Description
1M x 36/2M x 18 Pipelined DCD SRAM
CY7C1444V33 Vendor
Cypress
CY7C1444V33 Categories
1Mx36 SRAM
CY7C1444V33 Features
Fast clock speed: 250, 200, and 167 MHz Provide high-performance 3-1-1-1 access rate Fast access time: 2.7, 3.0 and 3.5 ns Optimal for depth expansion Single 3.3V –5% and +5% power supply V_DD Separate V_DDQ for 3.3V or 2.5V Common data inputs and data outputs Byte Write Enable and Global Write control Chip enable for address pipeline Address, data, and control registers Internally self-timed Write Cycle Burst control pins (interleaved or linear burst sequence) Automatic power-down for portable applications High-density, high-speed packages JTAG boundary scan for BGA packaging version Available in 119-ball bump BGA,165-ball FBGA and 100-pin TQFP packages (CY7C1444V33 and CY7C1445V33)
CY7C1444V33 Description
The Cypress Synchronous Burst SRAM family employs high-speed, low-power CMOS designs using advanced single-layer polysilicon, triple-layer metal technology. Each memory cell consists of six transistors. The CY7C1444V33 and CY7C1445V33 SRAMs integrate 1,048,576 x 36/2,097,152 x18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). The synchronous inputs include all addresses, all data inputs, address-pipelining Chip Enable (/CE), burst control inputs (/ADSC, /ADSP, and /ADV), write enables (/BWa, /BWb, /BWc, /BWd and /BWE), and Global Write (/GW). Asynchronous inputs include the Output Enable (/OE) and burst mode control (MODE). The data (DQ_a,b,c,d) and the data parity (DP_a,b,c,d) outputs, enabled by /OE, are also asynchronous. DQ_a,b,c,d and DP_a,b,c,d apply to CY7C1444V33 , and DQ_a,b and DP_a,b apply to CY7C1445V33. a, b, c, d each are eight bits wide in the case of DQ and 1 bit wide in the case of DP. Addresses and chip enables are registered with either Address Status Processor (/ADSP) or Address Status Controller (/ADSC) input pins. Subsequent burst addresses can be internally generated as controlled by the Burst Advance Pin (/ADV). Address, data inputs, and write controls are registered on-chip to initiate self-timed WRITE cycle. WRITE cycles can be one to four bytes wide as controlled by the write control inputs. Individual byte write allows individual byte to be written. /BWa controls DQa and DPa. /BWb controls DQb and DPb. /BWc controls DQc and DPd. /BWd controls DQ and DPd. /BWa, /BWb, /BWc, /BWd can be active only with /BWE being LOW. /GW being LOW causes all bytes to be written. WRITE pass-through capability allows written data available at the output for the immediately next READ cycle. This device also incorporates pipelined enable circuit for easy depth expansion without penalizing system performance. The CY7C1444V33/CY7C1445V33 are both double-cycle deselect parts.All inputs and outputs of the CY7C1444V33, CY7C1445V33 are JEDEC-standard JESD8-5-compatible.

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