CY7C1460V33

CY7C1460V33 Manufacturer

CY7C1460V33 Description

CY7C1460V33 Categories

CY7C1460V33 Price & Availability

CY7C1460V33 Features

• Zero Bus Latency^TM, no dead cycles between write and read cycles
• Fast clock speed: 250, 200, and 167 MHz
• Fast access time: 2.7, 3.0 and 3.5 ns
• Internally synchronized registered outputs eliminate the need to control /OE
• Single 3.3V ?5% and +5% power supply V_DD
• Separate V_DDQ for 3.3V or 2.5V
• Single /WE (Read/Write) control pin
• Positive clock-edge triggered, address, data, and control signal registers for fully pipelined applications
• Interleaved or linear four-word burst capability
• Individual byte write (/BWS_a? /BWS_h) control (may be tied LOW)
• /CEN pin to enable clock and suspend operations
• Three chip enables for simple depth expansion
• JTAG boundary scan for BGA packaging version
• Available in 119-ball bump BGA, 165-ball FBGA package and 100-pin TQFP packages (CY7C1460 and CY7C1462). 209 FBGA package for CY7C1464

CY7C1460V33 Description

The CY7C1460V33, CY7C1462V33, and CY7C1464V33 SRAMs are designed to eliminate dead cycles when transitions from READ to WRITE or vice versa. These SRAMs are optimized for 100 percent bus utilization and achieves Zero Bus Latency. They integrate 1,048,576 x 36/2,097,152 x 18/ 524,288 x 72 SRAM cells, respectively, with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. The Synchronous Burst SRAM family employs high-speed, low-power CMOS designs using advanced single-layer polysilicon, three-layer metal technology. Each memory cell consists of six transistors.

All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). The synchronous inputs include all addresses, all data inputs, depth-expansion Chip Enables (/CE₁, CE₂, and /CE₃), cycle start input (ADV//LD), Clock Enable (/CEN), Byte Write Selects (/BWS_a, /BWS_b, /BWS_c , /BWS_d, /BWS_e, /BWS_f, /BWS_g, /BWS_h), and read-write control (/WE). /BWS_c and /BWS_d apply to CY7C1460V33 and CY7C1464V33 only. /BWS_e, /BWS_f, /BWS_g, and /BWS_h apply to CY7C1464V33 only.

Address and control signals are applied to the SRAM during one clock cycle, and two cycles later, its associated data occurs, either read or write.

A Clock Enable (/CEN) pin allows operation of the CY7C1460V33, CY7C1462V33, and CY7C1464V33 to be suspended as long as necessary. All synchronous inputs are ignored when (/CEN) is high and the internal device registers will hold their previous values.

There are three Chip Enable (/CE₁, CE₂, /CE₃) pins that allow the user to deselect the device when desired. If any one of these three are not active when ADV//LD is low, no new memory operation can be initiated and any burst cycle in progress is stopped. However, any pending data transfer