The CY7C1461V25,CY7C1463V25 and CY7C1465V25 SRAMs are designed to eliminate dead cycles when transitions from Read to Write or vice versa. These SRAMs are optimized for 100 percent bus utilization and achieves Zero Bus Latency. They integrate 1,048,576 x 36/2,097,152 x 18/ 524,288 x 72 SRAM cells, respectively, with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. The Synchronous Burst SRAM family employs high-speed, low-power CMOS designs using advanced single layer polysilicon, threelayer metal technology. Each memory cell consists of six transistors.

All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). The synchronous inputs include all addresses, all data inputs, depth-expansion Chip Enables (/CE₁, CE₂, and /CE₃), cycle start input (ADV//LD), Clock Enable (/CEN), Byte Write Selects (/BWS_a, /BWS_b, /BWS_c, /BWS_d, /BWS_e, /BWS_f, /BWS_g, /BWS_h), and read-write control (/WE). /BWS_c and /BWS_d apply to CY7C1461V25 and CY7C1465V25 only. /BWS_e, /BWS_f, /BWS_g, and /BWS_h apply to CY7C1465V25 only.

A Clock Enable (/CEN) pin allows operation of the CY7C1461V25, CY7C1463V25 and CY7C1465V25 to be suspended as long as necessary. All synchronous inputs are ignored when (/CEN) is high and the internal device registers will hold their previous values.

There are three Chip Enable (/CE₁, CE₂, /CE₃) pins that allow the user to deselect the device when desired. If any one of these three are not active when ADV//LD is low, no new memory operation can be initiated and any burst cycle in progress is stopped. However, any pending data transfers (read or write) will be completed. The data bus will be in high impedance state two cycles after chip is deselected or a write cycle is initiated.

The CY7C1461V25, CY7C1463V25 and CY7C1465V25 have an on-chip two-bit burst counter. In the burst mode, CY7C1461V25,CY7C1463V25 and CY7C1465V25 provide four cycles of data for a single address presented to the SRAM. The order of the burst sequence is defined by the MODE input pin. The MODE pin selects between linear and interleaved burst sequence. The ADV//LD signal is used to load a new external address (ADV//LD = LOW) or increment the internal burst counter (ADV//LD = HIGH)

Output Enable (/OE) and burst sequence select (MODE) are the asynchronous signals. /OE can be used to disable the outputs at any given time. ZZ may be tied to LOW if it is not used.

Four pins are used to implement JTAG test capabilities. The JTAG circuitry is used to serially shift data to and from the device. JTAG inputs use LVTTL/LVCMOS levels to shift data during this testing mode of operation.