CY7C1465V25

CY7C1465V25 Manufacturer

CY7C1465V25 Description

CY7C1465V25 Categories

CY7C1465V25 Price & Availability

CY7C1465V25 Features

• Zero Bus Latency^TM, no dead cycles between write and read cycles
• Supports 133-MHz bus operations
• 1M x 36/2M x18/512K x 72 common I/O
• Fast clock-to-output times
  • 6.5 ns (for 133-MHz device)
  • 7.5 ns (for 117-MHz device)

CY7C1465V25 Description

The CY7C1461V25,CY7C1463V25 and CY7C1465V25 SRAMs are designed to eliminate dead cycles when transitions from Read to Write or vice versa. These SRAMs are optimized for 100 percent bus utilization and achieves Zero Bus Latency. They integrate 1,048,576 x 36/2,097,152 x 18/ 524,288 x 72 SRAM cells, respectively, with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. The Synchronous Burst SRAM family employs high-speed, low-power CMOS designs using advanced single layer polysilicon, threelayer metal technology. Each memory cell consists of six transistors.

All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). The synchronous inputs include all addresses, all data inputs, depth-expansion Chip Enables (/CE₁, CE₂, and /CE₃), cycle start input (ADV//LD), Clock Enable (/CEN), Byte Write Selects (/BWS_a, /BWS_b, /BWS_c, /BWS_d, /BWS_e, /BWS_f, /BWS_g, /BWS_h), and read-write control (/WE). /BWS_c and /BWS_d apply to CY7C1461V25 and CY7C1465V25 only. /BWS_e, /BWS_f, /BWS_g, and /BWS_h apply to CY7C1465V25 only.

A Clock Enable (/CEN) pin allows operation of the CY7C1461V25, CY7C1463V25 and CY7C1465V25 to be suspended as long as necessary. All synchronous inputs are ignored when (/CEN) is high and the internal device registers will hold their previous values.

There are three Chip Enable (/CE₁, CE₂, /CE₃) pins that allow the user to deselect the device when desired. If any one of these three are not active when ADV//LD is low, no new memory operation can be initiated and any burst cycle in progress is stopped. However, any pending data transfers (read or write) will be completed. The data bus will be in high impedance state two cycles after chip is deselected or a write cycle is initiated.

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