CY7C1470V33-200AXCES

CY7C1470V33-200AXCES Manufacturer

CY7C1470V33-200AXCES Description

CY7C1470V33-200AXCES Datasheet (PDF)

CY7C1470V33-200AXCES Price & Availability

CY7C1470V33-200AXCES Features

• Pin-compatible and functionally equivalent to ZBT?
• Supports 225-MHz bus operations with zero wait states
  • Available speed grades are 225-, 200-, and 167-MHz
• Internally self-timed output buffer control to eliminate the need to use asynchronous /OE
• Fully registered (inputs and outputs) for pipelined operation
• Byte Write capability
• Single 3.3V power supply
• 3.3V/2.5V I/O power supply
• Fast clock-to-output time
  • 3.0 ns (for 225-MHz device)
  • 3.0 ns (for 200-MHz device)
  • 3.4 ns (for 167-MHz device)
• Clock Enable (/CEN) pin to suspend operation
• Synchronous self-timed writes
• CY7C1470V33 and CY7C1472V33 available in 100 TQFP, and 165-ball fBGA packages. CY7C1474V33 available in 209-ball fBGA package
• IEEE 1149.1 JTAG Boundary Scan compatible
• Burst capability?linear or interleaved burst order ?ZZ?
• Sleep Mode option and Stop Clock option

CY7C1470V33-200AXCES Description

The CY7C1470V33, CY7C1472V33, and CY7C1474V33 are 3.3V, 2M x 36/4M x 18/1M x 72 Synchronous pipelined burst SRAMs with No Bus Latency? (NoBL.) logic, respectively. They are designed to support unlimited true back-to-back Read/Write operations with no wait states. The CY7C1470V33, CY7C1472V33, and CY7C1474V33 are equipped with the advanced (NoBL) logic required to enable consecutive Read/Write operations with data being transferred on every clock cycle. This feature dramatically improves the throughput of data in systems that require frequent Write/Read transitions. The CY7C1470V33, CY7C1472V33, and CY7C1474V33 are pin compatible and functionally equivalent to ZBT devices.

All synchronous inputs pass through input registers controlled by the rising edge of the clock. All data outputs pass through output registers controlled by the rising edge of the clock. The clock input is qualified by the Clock Enable (/CEN) signal, which when deasserted suspends operation and extends the previous clock cycle.

Write operations are controlled by the Byte Write Selects (/BWa?/BWh for CY7C1474V33, /BWa?/BWd for CY7C1470V33 and /BWa?/BWb for CY7C1472V33) and a Write Enable (/WE) input. All writes are conducted with on-chip synchronous self-timed write circuitry.

CY7C1470V33-200AXCES Parameters

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