CY7C1471V25

CY7C1471V25 Manufacturer

CY7C1471V25 Description

CY7C1471V25 Categories

CY7C1471V25 Datasheet (PDF)

CY7C1471V25 Price & Availability

CY7C1471V25 Features

• No Bus Latency? (NoBL?) architecture eliminates
• dead cycles between write and read cycles.
• Can support up to 133-MHz bus operations with zero wait states
• Data is transferred on every clock
• Pin compatible and functionally equivalent to ZBT? devices
• Internally self-timed output buffer control to eliminate the need to use /OE
• Registered inputs for flow-through operation
• Byte Write capability
• 2.5V/1.8V I/O power supply
• Fast clock-to-output times
  • 6.5 ns (for 133-MHz device)
  • 7.5 ns (for 117-MHz device)
  • 8.5 ns (for 100-MHz device)
• Clock Enable (/CEN) pin to enable clock and suspend operation
• Synchronous self-timed writes
• Asynchronous Output Enable
• Offered in JEDEC-standard 100 TQFP, and 165-ball fBGA packages for CY7C1471V25 and CY7C1473V25.
• 209-ball fBGA package for CY7C1475V25.
• Three chip enables for simple depth expansion.
• Automatic Power-down feature available using ZZ mode or CE deselect.
• JTAG boundary scan for BGA and fBGA packages Burst Capability?linear or interleaved burst order
• Low standby power

CY7C1471V25 Description

The CY7C1471V25, CY7C1473V25 and CY7C1475V25 are 2.5V, 2M x 36/4M x 18/1M x 72 Synchronous Flow-through Burst SRAMs designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1471V25, CY7C1473V25 and CY7C1475V25 are equipped with the advanced No Bus Latency (NoBL) logic required to enable consecutive Read/Write operations with data being transferred on every clock cycle. This feature dramatically improves the throughput of data through the SRAM, especially in systems that require frequent Write-Read transitions.

All synchronous inputs pass through input registers controlled by the rising edge of the clock. The clock input is qualified by the Clock Enable (/CEN) signal, which when deasserted suspends operation and extends the previous clock cycle. Maximum access delay from the clock rise is 6.5 ns (133-MHz device).

Write operations are controlled by the two or four Byte Write Select (/BWX) and a Write Enable (/WE) input. All writes are conducted with on-chip synchronous self-timed write circuitry.

Products Similar to CY7C1471V25