The CY7C1470V33, CY7C1472V33, and CY7C1474V33 are 3.3V, 2M x 36 / 4M x 18 / 1M x 72 Synchronous pipelined burst SRAMs with No Bus Latency™ (NoBLä) logic, respectively. They are designed to support unlimited true back-to-back Read/Write operations with no wait states. The CY7C1470V33, CY7C1472V33 and CY7C1474V33 are equipped with the advanced (NoBL) logic required to enable consecutive Read/Write operations with data being trans­ferred on every clock cycle. This feature dramatically improves the throughput of data in systems that require frequent Write/Read transitions. The CY7C1470V33, CY7C1472V33, and CY7C1474V33 are pin compatible and functionally equiv­alent to ZBT devices.

All synchronous inputs pass through input registers controlled by the rising edge of the clock. All data outputs pass through output registers controlled by the rising edge of the clock. The clock input is qualified by the Clock Enable (/CEN) signal, which when deasserted suspends operation and extends the previous clock cycle.

Write operations are controlled by the Byte Write Selects (/BW_a–/BW_h for CY7C1474V33, /BW_a–/BW_d for CY7C1470V33 and /BW_a–/BW_b for CY7C1472V33) and a Write Enable (/WE) input. All writes are onducted with on-chip synchronous self-timed write circuitry.

Three synchronous Chip Enables (/CE₁, CE₂, /CE₃) and an asynchronous Output Enable (/OE) provide for easy bank selection and output tri-state control. In order to avoid bus contention, the output drivers are synchronously tri-stated during the data portion of a write sequence.