CY7C1483V33-133AXC

CY7C1483V33-133AXC Manufacturer

CY7C1483V33-133AXC Description

CY7C1483V33-133AXC Datasheet (PDF)

CY7C1483V33-133AXC Price & Availability

CY7C1483V33-133AXC Features

• Supports 133-MHz bus operations
• 2M x 36/4M x 18/1M x 72 common I/O
• Fast clock-to-output times
• 5.5 ns (for 150-MHz device)
• 6.5 ns (for 133-MHz device)
• 7.5 ns (for 117-MHz device)
• 8.5 ns (for 100-MHz device)
• Single 3.3V ?5% and +5% power supply V_DD
• Separate V_DDQ for 3.3V or 2.5V
• Byte Write
• Enable and Global Write control
• Burst Capability linear or interleaved burst order
• Automatic power-down available using ZZ mode or /CE deselect
• JTAG boundary scan for BGA packaging version
• Available in 119-ball bump BGA and 100-pin TQFP packages (CY7C1481V33 and CY7C1483V33). 209 BGA package for CY7C1487V33
• 165-ball FBGA and 209-ball BGA will only be offered on an opportunity basis (check with Cypress sales and marketing)

CY7C1483V33-133AXC Description

The Cypress Synchronous Burst SRAM family employs high-speed, low power CMOS designs using advanced single-layer polysilicon, triple-layer metal technology. Each memory cell consists of six transistors.

The CY7C1481V33/CY7C1483V33/CY7C1487V33 SRAMs integrate 2,097,152 x 36 / 4,194,304 x18 and 1,048,576x 72 SRAM cells with advanced synchronous peripheral circuitry and a 2-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered clock input (CLK). The synchronous inputs include all addresses, all data inputs, address-pipelining Chip Enable (/CE), Burst Control Inputs (/ADSC, /ADSP, and /ADV), Write Enables (/BW_a, /BW_b, /BW_c, /BW_d, /BW_e, /BW_f, /BW_g, /BW_h, and /BWE), and Global Write (/GW).

Asynchronous inputs include the Output Enable (/OE) and Burst Mode Control (MODE). The data outputs (Q), enabled by OE, are also asynchronous.

Addresses and chip enables are registered with either Address Status Processor (/ADSP) or address status controller (/ADSC) input pins. Subsequent burst addresses can be internally generated as controlled by the Burst Advance Pin (/ADV).

Address, data inputs, and write controls are registered on-chip to initiate self-timed WRITE cycle. WRITE cycles can be one to four bytes wide as controlled by the write control inputs. Individual byte write allows individual byte to be written. /BW_a controls DQ_a and DP_a. /BW_b controls DQ_b and DP_b. /BW_c controls DQ_c and DP_c. /BW_d controls DQ_d and DP_d. /BW_e controls DQ_e and DP_e. /BW_f controls DQ_f and DP_f. /BW_g controls DQ_g and DP_g. /BW_h controls DQ_h and DP_h. /BW_a, /BW_b, /BW

CY7C1483V33-133AXC Parameters

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