The Cypress Synchronous Burst SRAM family employs high-speed, low power CMOS designs using advanced single-layer polysilicon, triple-layer metal technology. Each memory cell consists of six transistors.

The CY7C1481V33/CY7C1483V33/CY7C1487V33 SRAMs integrate 2,097,152 x 36 / 4,194,304 x18 and 1,048,576x 72 SRAM cells with advanced synchronous peripheral circuitry and a 2-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered clock input (CLK). The synchronous inputs include all addresses, all data inputs, address-pipelining Chip Enable (/CE), Burst Control Inputs (/ADSC, /ADSP, and /ADV), Write Enables (/BW_a, /BW_b, /BW_c, /BW_d, /BW_e, /BW_f, /BW_g, /BW_h, and /BWE), and Global Write (/GW).

Asynchronous inputs include the Output Enable (/OE) and Burst Mode Control (MODE). The data outputs (Q), enabled by OE, are also asynchronous.

Addresses and chip enables are registered with either Address Status Processor (/ADSP) or address status controller (/ADSC) input pins. Subsequent burst addresses can be internally generated as controlled by the Burst Advance Pin (/ADV).

Address, data inputs, and write controls are registered on-chip to initiate self-timed WRITE cycle. WRITE cycles can be one to four bytes wide as controlled by the write control inputs. Individual byte write allows individual byte to be written. /BW_a controls DQ_a and DP_a. /BW_b controls DQ_b and DP_b. /BW_c controls DQ_c and DP_c. /BW_d controls DQ_d and DP_d. /BW_e controls DQ_e and DP_e. /BW_f controls DQ_f and DP_f. /BW_g controls DQ_g and DP_g. /BW_h controls DQ_h and DP_h. /BW_a, /BW_b, /BW_c, /BW_d, /BW_e, /BW_f, /BW_g, and /BW_h can be active only with /BWE LOW. GW being LOW causes all bytes to be written. WRITE pass-through capability allows written data available at the output for the immediately next READ cycle. This device also incorporates pipelined enable circuit for easy depth expansion without penalizing system performance.

Inputs and outputs of the CY7C1481V33/CY7C1483V33/ CY7C1487V33 are JEDEC-standard JESD8-5-compatible.