CY7C1484V33

CY7C1484V33 Manufacturer

CY7C1484V33 Description

CY7C1484V33 Categories

CY7C1484V33 Datasheet (PDF)

CY7C1484V33 Price & Availability

CY7C1484V33 Features

• Supports bus operation up to 225 MHz
• Available speed grades are 225, 200 and 167 MHz
• Registered inputs and outputs for pipelined operation
• Optimal for performance (Double-Cycle deselect)
• Depth expansion without wait state
• 3.3V ?5% and +10% core power supply (VDD)
• 2.5V / 3.3V I/O operation
• Fast clock-to-output times
  • 3.0 ns (for 225-MHz device)
  • 3.0 ns (for 200-MHz device)
  • 3.4 ns (for 167-MHz device)
• Provide high-performance 3-1-1-1 access rate
• User-selectable burst counter supporting Intel. Pentium interleaved or linear burst sequences
• Separate processor and controller address strobes
• Synchronous self-timed writes
• Asynchronous output enable
• Offered in JEDEC-standard 100-pin TQFP and 165-Ball fBGA packages
• IEEE 1149.1 JTAG-Compatible Boundary Scan
• ?ZZ? Sleep Mode Option

CY7C1484V33 Description

The CY7C1484V33/CY7C1485V33 SRAM integrates 2,097,152 x 36/4,194,304 x 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). The synchronous inputs include all addresses, all data inputs, address-pipelining Chip Enable (/CE1), depth-expansion Chip Enables (CE2 and /CE3 ), Burst Control inputs (/ADSC, /ADSP, and /ADV), Write Enables (/BWX, and /BWE), and Global Write (/GW). Asynchronous inputs include the Output Enable (/OE) and the ZZ pin.

Addresses and chip enables are registered at rising edge of clock when either Address Strobe Processor (/ADSP) or Address Strobe Controller (/ADSC) are active. Subsequent burst addresses can be internally generated as controlled by the Advance pin (/ADV).

Address, data inputs, and write controls are registered on-chip to initiate a self-timed Write cycle. This part supports Byte Write operations (see Pin Descriptions and Truth Table for further details). Write cycles can be one to four bytes wide as controlled by the byte write control inputs. /GW active LOW causes all bytes to be written. This device incorporates an additional pipelined enable register which delays turning off the output buffers an additional cycle when a deselect is executed. This feature allows depth expansion without penalizing system performance.

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