The CY7C42X5V are high-speed, low-power, first-in first-out (FIFO) memories with clocked read and write interfaces. All are 18 bits wide. The CY7C42X5V can be cascaded to increase FIFO depth. Programmable features include Almost Full/Almost Empty flags. These FIFOs provide solutions for a wide variety of data buffering needs, including high-speed data acquisition, multiprocessor interfaces, and communications buffering. These FIFOs have 18-bit input and output ports that are controlled by separate clock and enable signals. The input port is controlled by a Free-Running Clock (WCLK) and a Write Enable pin (/WEN). When /WEN is asserted, data is written into the FIFO on the rising edge of the WCLK signal. While /WEN is held active, data is continually written into the FIFO on each cycle. The output port is controlled in a similar manner by a Free-Running Read Clock (RCLK) and a Read Enable pin (/REN). In addition, the CY7C42X5V have an Output Enable pin (/OE). The read and write clocks may be tied together for single-clock operation or the two clocks may be run independently for asynchronous read/write applications. Clock frequencies up to 66 MHz are achievable. Retransmit and Synchronous Almost Full/Almost Empty flag features are available on these devices. Depth expansion is possible using the Cascade Input (/WXI, /RXI), Cascade Output (/WXO, /RXO), and First Load (/FL) pins. The /WXO and /RXO pins are connected to the /WXI and /RXI pins of the next device, and the /WXO and /RXO pins of the last device should be connected to the /WXI and /RXI pins of the first device. The /FL pin of the first device is tied to VSS and the /FL pin of all the remaining devices should be tied to VCC. The CY7C42X5V provides five status pins. These pins are decoded to determine one of five states: Empty, Almost Empty, Half Full, Almost Full, and Full (see Table 2). The Half Full flag shares the /WXO pin. This flag is valid in the stand-alone and width-expansion configurati |