| 100331QC Description |
| Low Power Triple D-Type Flip-Flop |
| 100331QC Vendor |
| Fairchild Semiconductor |
| 100331QC Features |
- 35% power reduction of the 100131
- 2000V ESD protection
- Pin/function compatible with 100131
- Voltage compensated operating range = -4.2V to -5.7V
- Available to industrial grade temperature range
|
| 100331QC Description |
The 100331 contains three D-type, edge-triggered master/slave flip-flops with true and complement outputs, a Common Clock (CPC), and Master Set (MS) and Master Reset (MR) inputs. Each flip-flop has individual Clock (CPn), Direct Set (SDn) and Direct Clear (CDn) inputs. Data enters a master when both CPn and CPC are LOW and transfers to a slave when CPn or CPC (or both) go HIGH. The Master Set, Master Reset and individual CDn and SDn inputs override the Clock inputs. All inputs have 50 kohm pull-down resistors. |
| 100331QC Datasheet and Application Notes |
|
| Parameter | Value |
| Product status | Not recommended for new designs |
| Package type | DIP |
| Leads | 24 |
| Packing method | RAIL |
| Product status | Not recommended for new designs |
| Package type | PLCC |
| Leads | 28 |
| Packing method | RAIL |
| Products related to 100331QC |
100331QIX 100331SC 100331QCX 100331PC
100331 100331QI 100331SCX |